DESIGNING TCP/IP CHECKSUM FUNCTION FOR ACCELERATION IN FPGA

Authors

  • EB Eyo Department of Electronic Engineering University of Nigeria, Nsukka
  • TA Nwodoh Department of Electronic Engineering University of Nigeria, Nsukka

DOI:

https://doi.org/10.4314/njt.293.1038

Keywords:

FPGA, TCP/IP, CPU, Checksum, VHDL, Timing simulation, Throughput

Abstract

Over the years network transmission speeds have improved greatly without a corresponding
increase in the processing speed of the host processor. Traditionally, n etwork protocol
processing is handled in the CPU of the host computer. However, with devices featuring
advanced connectivity and Internet functionality, protocol processing has created a heavy
workload on the general processing processors, with additional constraints by the slower I/O
bus speed limits. Consequently, for a higher throughput and speedy delivery of information
between hosts on the internet, there is the need to identify those performance -critical TCP/IP
functions and accelerate them in order to match the transmission speeds with the protocol
processing speeds. Based on profiling results, a micro-level function, namely checksum is
observed to be a computational intensive function. In this paper, the checksum function is
selected and implemented in an FPGA. The checksum calculation is implemented based on 16 -
bit one’s complement adders. In all, by minimizing the functional overhead, such as , instruction fetching and decoding, bus speed constraints, latency due to buffer/memory transfer; and providing flexibility by configuration possibilities, the high speed and cost
advantage are made possible.

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Section

Research papers of General Interest

How to Cite

DESIGNING TCP/IP CHECKSUM FUNCTION FOR ACCELERATION IN FPGA. (2009). Nigerian Journal of Technology, 29(3), 31-41. https://doi.org/10.4314/njt.293.1038